SK hynix will mass-produce LPDDR6 in the second half of this year, and the first customer is China's Xiaomi. Development finished in March, and the part is built on a 10nm-class sixth-generation (1c) process — as reported exclusively by Herald Business.
The standard itself was settled a year earlier. JEDEC published the LPDDR6 specification (JESD209-6) on 10 July 2025, with per-pin rates starting at 10.667 Gbps and reaching 14.4 Gbps. Against LPDDR5X's 8.533 Gbps, the top end is 1.69 times higher. But that figure is not what sizes the generational jump. Widening the channel from 16 bits to 24 moves system bandwidth further than the pin rate does.
Where LPDDR6 parts ways with LPDDR5X
The JESD209-6 structure summarised by StorageNewsletter is two sub-channels per die with twelve data lines (DQs) each. Two twelve-bit halves make a 24-bit channel, and access granularity supports both 32 bytes and 64 bytes. LPDDR5 and 5X ran 16-bit channels, so a single channel now carries 1.5 times as much per transfer.
Laid side by side, the changed items look like this.
| Item | LPDDR5X | LPDDR6 |
|---|---|---|
| Per-pin rate (Gbps) | up to 8.533 | 10.667 – 14.4 |
| Channel width (bit) | 16 | 24 |
| Sub-channel layout | - | 2 per die, 12 DQs per sub-channel |
| Access granularity | - | 32 bytes / 64 bytes |
| Supply and power | - | low-voltage VDD2, dynamic voltage-frequency scaling (DVFSL) |
| Reliability features | - | on-die ECC, PRAC, CA parity, MBIST, programmable link protection |
The line that stands out is the last one. On-die ECC, PRAC (row-activation-counter protection) and CA parity are server DRAM vocabulary. Their arrival in a mobile specification says LPDDR6 was designed on the assumption that it would leave the phone.
How many GB/s is that, worked out
Gbps describes one pin; what anyone actually feels is the bytes per second across the whole bus. The conversion is simple — bandwidth (GB/s) = per-pin rate (Gbps) × bus width (bit) ÷ 8. Below it is computed per channel and per smartphone bus, using the widening path reported by Tom's Hardware (64 to 96 bits in phones, 128 to 192 bits in laptops).
| Case | Per-pin rate (Gbps) | Channel width (bit) | Per-channel (GB/s) | Phone bus (bit) | Bus bandwidth (GB/s) |
|---|---|---|---|---|---|
| LPDDR5X top | 8.533 | 16 | 17.1 | 64 | 68.3 |
| LPDDR6 low | 10.667 | 24 | 32.0 | 96 | 128.0 |
| LPDDR6 mid | 12.8 | 24 | 38.4 | 96 | 153.6 |
| LPDDR6 top | 14.4 | 24 | 43.2 | 96 | 172.8 |
On pin rate alone, 8.533 to 14.4 is a 1.69x step. Fold in the wider channel and bus bandwidth goes from 68.3 to 172.8 GB/s — 2.53x. That is why the phrase "double the effective bandwidth" is not marketing inflation.
It is worth checking the quoted numbers. Tom's Hardware pairs a maximum of 38.4 GB/s with a 64-bit bus, but run it through the formula and 38.4 is what a 24-bit channel at 12.8 Gbps produces. A 64-bit bus at 14.4 Gbps would be 115.2 GB/s. When a GB/s figure appears in coverage, the first question is whether it describes a channel or a bus.
The size of a generation change comes from the channel width multiplied by the pin rate — that single move to 24 bits does more than going from 8.533 to 14.4.
Why a mobile standard keeps showing up in AI server news
What changed LPDDR's weight was the server, not the phone. On 20 April, SK hynix announced mass production of a 192GB SOCAMM2 built on LPDDR5X, citing twice the bandwidth of conventional RDIMM and a 75% improvement in energy efficiency. Samsung claims more than double the bandwidth of RDIMM at 55% or less of the power for the same format, with up to 153.6 GB/s per module.
SOCAMM, in other words, is mobile low-power DRAM repackaged as a server module — and the silicon inside it is next in line to move from LPDDR5X to LPDDR6. That is the backdrop to Herald Business expecting SOCAMM competition among the three memory makers (Samsung, SK hynix, Micron) to intensify. It also means the mobile DRAM cycle is no longer a function of smartphone unit sales alone.
What the choice of Xiaomi tells you
Where early production volume goes is an indirect read on process health. LPDDR6 comes off the 1c node, the same generation used for SOCAMM2. When a new standard rides a new process and the first volume points at one customer, two readings are available: that demand worth prioritising leading-edge output has been secured, or that a partner was chosen to share the heavy qualification burden of the opening phase.
The conditions under which that reading fails are equally clear. First, if the Xiaomi flagship schedule slips, early volume sits as inventory and a supply win does not become revenue. Second, if a rival clears LPDDR6 qualification in the same quarter, first-mover position never converts into pricing power. Third, if SOCAMM adoption lags, the server axis moves out to the following generation. Separating a single headline from a cycle follows the same frame set out in the piece on telling a dead cat bounce from a trend change.
What to watch
- A firm production date — whether "second half" means Q3 or Q4. First shipment recognition touches earnings, not the supply announcement.
- The 1c mix — how fast the 10nm-class sixth-generation share climbs in quarterly disclosures. LPDDR6 and SOCAMM2 draw on the same node.
- Customer diversification — whether phone and laptop customers beyond Xiaomi sign on. A long single-customer stretch caps pricing power.
- Rival qualification progress — when Samsung and Micron announce LPDDR6 completion and qualification. Overlap in the same quarter makes the premium short-lived.
- SOCAMM moving to LPDDR6 — today's SOCAMM2 is LPDDR5X-based. The announcement of an LPDDR6 module is where the server axis actually begins.
- Whether buses widen — whether shipping application processors and platforms adopt the 96-bit bus. That is where the channel-width gain gets confirmed.
- How disclosures phrase it — check whether a bandwidth figure is per channel or per bus. Numbers that fail the formula above usually belong to a different unit. The reading order for earnings material is the same one used for EPS, guidance and consensus.